Controller descriptor. This structure represents the common (controller-independent) part of a controller for the USB code. The corresponding controller-dependent part *hci_controller is located immediately before usb_controller. More...

Public Attributes
dd	Next

dd	Prev

dd	HardwareFunc

dd	NumPorts

dd	PCICoordinates

dd	WaitPipeListAsync

dd	WaitPipeListPeriodic

dd	WaitPipeRequestAsync

dd	WaitPipeRequestPeriodic

dd	ReadyPipeHeadAsync

dd	ReadyPipeHeadPeriodic

dd	NewConnected

dd	NewDisconnected

dd	PendingPorts

MUTEX	ControlLock

MUTEX	BulkLock

MUTEX	PeriodicLock

dd	StartWaitFrame

dd	ResettingHub

db	ResettingPort

db	ResettingSpeed

db	ResettingStatus

dd	ResetTime

rb	SetAddressBuffer

rd	ExistingAddresses

rd	ConnectedTime

rd	DevicesByPort

Detailed Description

Controller descriptor. This structure represents the common (controller-independent) part of a controller for the USB code. The corresponding controller-dependent part *hci_controller is located immediately before usb_controller.

Source: bus/usb/common.inc:180

Member Data Documentation

◆ BulkLock

MUTEX usb_controller::BulkLock

mutex which guards all operations with control queue

◆ ConnectedTime

rd usb_controller::ConnectedTime

Bitmask for 128 bits; bit i is cleared <=> address i is free for allocating for new devices. Bit 0 is always set.

◆ ControlLock

MUTEX usb_controller::ControlLock

bit mask of ports which are ready to be initialized

◆ DevicesByPort

rd usb_controller::DevicesByPort

Time, in timer ticks, when the port i has signalled the connect event. Valid only if bit i in NewConnected is set.

◆ ExistingAddresses

rd usb_controller::ExistingAddresses

Buffer for USB control command SET_ADDRESS.

◆ HardwareFunc

dd usb_controller::HardwareFunc

◆ NewConnected

dd usb_controller::NewConnected

Items of RemovingList* which were released by hardware and are ready for further processing. (Pointers to some items in WaitPipeList* or NULLs).

◆ NewDisconnected

dd usb_controller::NewDisconnected

bit mask of recently connected ports of the root hub, bit set = a device was recently connected to the corresponding port; after USB_CONNECT_DELAY ticks of stable status these ports are moved to PendingPorts

◆ Next

dd usb_controller::Next

Two following fields organize all controllers in the global linked list.

◆ NumPorts

dd usb_controller::NumPorts

Pointer to usb_hardware_func structure with controller-specific functions.

◆ PCICoordinates

dd usb_controller::PCICoordinates

Number of ports in the root hub.

◆ PendingPorts

dd usb_controller::PendingPorts

bit mask of disconnected ports of the root hub, bit set = a device in the corresponding port was disconnected, disconnect processing is required.

◆ PeriodicLock

MUTEX usb_controller::PeriodicLock

mutex which guards all operations with bulk queue

◆ Prev

dd usb_controller::Prev

◆ ReadyPipeHeadAsync

dd usb_controller::ReadyPipeHeadAsync

Pending request to hardware to refresh cache for items from WaitPipeList*. (Pointers to some items in WaitPipeList* or NULLs).

◆ ReadyPipeHeadPeriodic

dd usb_controller::ReadyPipeHeadPeriodic

◆ ResetTime

dd usb_controller::ResetTime

◆ ResettingHub

dd usb_controller::ResettingHub

USB frame number when WaitPipeRequest* was registered.

◆ ResettingPort

db usb_controller::ResettingPort

Pointer to usb_hub responsible for the currently resetting port, if any. NULL for the root hub.

◆ ResettingSpeed

db usb_controller::ResettingSpeed

Port that is currently resetting, 0-based.

◆ ResettingStatus

db usb_controller::ResettingStatus

Speed of currently resetting device.

◆ SetAddressBuffer

rb usb_controller::SetAddressBuffer

Time when reset signalling or reset recovery has been started.

◆ StartWaitFrame

dd usb_controller::StartWaitFrame

spinlock guarding WaitPipeRequest/ReadyPipeHead (but not WaitPipeList)

◆ WaitPipeListAsync

dd usb_controller::WaitPipeListAsync

Device:function and bus number from PCI.

The hardware is allowed to cache some data from hardware structures. Regular operations are designed considering this, but sometimes it is required to wait for synchronization of hardware cache with modified structures in memory. The code keeps two queues of pipes waiting for synchronization, one for asynchronous (bulk/control) pipes, one for periodic pipes, hardware cache is invalidated under different conditions for those types. Both queues are organized in the same way, as single-linked lists. There are three special positions: the head of list (new pipes are added here), the first pipe to be synchronized at the current iteration, the tail of list (all pipes starting from here are synchronized).

◆ WaitPipeListPeriodic

dd usb_controller::WaitPipeListPeriodic

◆ WaitPipeRequestAsync

dd usb_controller::WaitPipeRequestAsync

List heads.

◆ WaitPipeRequestPeriodic

dd usb_controller::WaitPipeRequestPeriodic

The documentation for this struct was generated from the following file:

bus/usb/common.inc

Public Attributes